Post by Woody
14336 on a 48K Speccy? This is from a real machine?
Sorry, I didn't explain that very well, and I was actually *wrong*
about floatspy. Thanks for making me think about it Woody!
On a real 48K Speccy, the ULA starts starts putting the Z80 under
contention 14336 T-states after the interrupt.
Because of this contention, the effects of writing to the first
display byte or border (even though it is invisible behind the
display) will be delayed a little.
Three T-states later (14339) the ULA reads the first display byte. It
is at T-state 14341 that the first top left hand display pixel is
output to the TV (the T-state after it has read the first Attribute
Floatspy returns first Display byte fetch at 14347 (8 Tstates later -
I thought they were accounting for the length of the IO instruction,
(14336+11) but as Woody has caused me to rethink this, I see that this
is not the case as the difference is 8. I dunno what Ramsoft are
thinking now ;-) )
[ It's time to run away if you're not interested in nerdy
A huge amount of analysis has shown that the precise timing of the IO/
Mem contention, byte fetches and pixel output is (first 4 bytes) :
14336 IO Contention Starts
14338 Memory Contention Starts
14339 First display byte fetch
14340 First attribute byte fetch
14341 IO Contention End, Border finish, 1st and 2nd pixels output to
screen, second display byte fetched from memory.
14342 Second attribute byte fetch, 3rd and 4th pixels output to screen
14343 Memory contention end, 5th and 6th pixels output to screen
14344 IO contention start, 7th and 8th pixels output to screen
14345 9th and 10th pixels output
14346 Memory contention starts, 11th and 12th pixels output to screen
14347 Display byte 3 fetch, 13th and 14th pixels output
14348 Attribute byte 3 fetch, 15th and 16th pixels output
14349 IO Contention End, Display byte 4 fetch, 17th and 18th pixel
14350 Attribute byte 4 fetch, 19th and 20th pixel output
The contention start and end T-states are inclusive, so the start and
end T-states experience contention, not the one following it. Note
also that the memory and IO contention periods are *different*.
It's a shame we can't analyse and compare this behaviour on a TSxxxx